1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly, to an integrated circuit which has a better ESD protection capability and is able to reduce circuit layout area.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 shows a simplified block diagram of a conventional integrated circuit 100, wherein the integrated circuit 100 can be applied to a communication device. As shown in FIG. 1, the integrated circuit 100 comprises: an internal circuit 102, a pad 104, a second resistance unit 106, and two first impedance matching units 110, wherein the two first impedance matching units 110 are connected in parallel with each other. The second resistance unit 106 is coupled between the pad 104 and the internal circuit 102, and connected in parallel with the two impedance matching units 110. Each impedance matching unit 110 is coupled between the internal circuit 102 and the pad 104, and each impedance matching unit 110 comprises: a switch unit 112 and a first resistance unit 114. The first resistance unit 114 is coupled between the first switch unit 112 and the internal circuit 102, and the switch unit 112 is directly electrically connected to the pad 104. Thus, the conventional integrated circuit 100 has a good linearity, however, the switch unit 112 will be directly damaged when ESD enters into the pad 104. In addition, when the switch unit 112 is realized by a MOS transistor switch, the ESD protection rules are required to be followed in the layout since the switch unit 112 is directly electrically connected to the pad 104. In this way, realizing the switch unit 112 with the MOS transistor switch requires a very large circuit layout area.
Please refer to FIG. 2. FIG. 2 shows a simplified block diagram of another conventional integrated circuit 200, wherein the integrated circuit 200 can be applied to a communication device. As shown in FIG. 2, the integrated circuit 200 comprises: an internal circuit 202, a first pad 204, a second pad 206, two first impedance matching units 210, two second impedance matching units 220, a third switch unit 230, a third resistance unit 240, and a fourth resistance unit 250, wherein the two first impedance matching units 210 are connected in parallel with each other, and the two second impedance matching units 220 are connected in parallel with each other. Each first impedance matching unit 210 is coupled between the internal circuit 202 and the first pad 204, and each first impedance matching unit 210 comprises: a first switch unit 212 and a first resistance unit 214, wherein the first switch unit 212 is directly electrically connected to the first pad 204. Each second impedance matching unit 220 is coupled between the internal circuit 202 and the second pad 206, and each second impedance matching unit 220 comprises: a second switch unit 222 and a second resistance unit 224, wherein the second switch unit 222 is directly electrically connected to the second pad 206. Similarly, the first switch unit 212 will be directly damaged when ESD enters into the first pad 204, and the second switch unit 222 will be directly damaged when ESD enters into the second pad 206. In addition, when the first switch unit 212 and the second switch unit 222 are respectively realized by a MOS transistor switch, the ESD protection rules are required to be followed in the layout since the first switch unit 212 and the second switch unit 222 are directly electrically connected to the first pad 204 and the second pad 206, respectively. In this way, realizing the first switch unit 212 and the second switch unit 222 with the MOS transistor switch respectively requires a very large circuit layout area. In addition, the integrated circuit 200 of the present invention can turn off the internal circuit 202 in certain power saving mode, and uses the third switch unit 230 to perform the function of impedance calibration, wherein the third switch unit 230 has very low power consumption. However, since the resistance value of two first impedance matching units 210 and the third resistance unit 240 connected in parallel with each other is very small, and the resistance value of two second impedance matching units 220 and the fourth resistance unit 250 connected in parallel with each other is also very small, the third switch unit 230 will be damaged easily and directly when ESD enters into the first pad 204 and/or the second pad 206.